1. Field of the Invention
The present invention generally relates to circuits for controlling memory access and processors and systems using such circuits, and particularly relates to a circuit for controlling a semaphore and a processor and system using such a circuit.
2. Description of the Related Art
In a system comprised of a plurality of processors, resources such as memories connected to a common bus are shared by the plurality of processors. When a given processor needs to use a memory, the processor may exclusively use the memory for a certain period of time. During such a time period, other processors are not allowed to access the memory. Such provision has to be made because system consistency cannot be maintained if memory access or data updating is performed by another processor during an ongoing transaction. In order to make exclusive use of shared resources, resource management based on use of semaphore registers is typically employed.
In the resource management based on the use of semaphore registers, a processor in need of exclusive use of a memory refers to a semaphore flag prior to accessing the memory. If the flag is not set, it is ascertained that other processors are not using the memory. In such a case, the processor sets the flag to explicitly indicate to other processors that the memory is going to be exclusively used, and then accesses the memory. During a time period in which the flag is in a set state, other processors cannot access the memory. After finishing the use of the memory, the processor that has been using the memory resets the semaphore flag.
In use of semaphore flags, it is necessary to implement strict flag management. Consideration is now given to a situation in which a processor refers to a semaphore flag and determines that the flag is not in a set state, followed by performing a flag setting operation to set the flag. If there is a time gap from the checking of the flag to the setting of the flag, another processor may refer to the semaphore flag during this time gap. In such a case, the processor that later referred to the semaphore flag ascertains that the memory is available because of the unset state of the flag.
In order to avoid such a situation, an access scheme called a read-modify-write access or an atomic-LOAD/STORE access is employed in referring to and setting a semaphore flag. In this access scheme, a read operation and a write operation are performed within a single bus cycle that is an indivisible unit of operation. Since a read operation and a write operation are performed within a single bus cycle to refer and set a flag, strict flag management becomes possible. In general, a processor that is designed for use in a multi-processor-system environment is equipped with the atomic-LOAD/STORE function as an access function.
General processors that are not specially designed for use in a multi-processor-system environment are not provided with such an atomic-LOAD/STORE function. In order to implement a multi-processor system by use of such general processors, certain consideration must be made in one way or another to provide the same or similar function as the atomic-LOAD/STORE function.
Accordingly, there is a need for a circuit that provides a function similar to the atomic-LOAD/STORE function when a multi-processor system is implemented by use of processors having no atomic-LOAD/STORE function. Further, there is a need for a processor and a multi-processor system that are provided with such a circuit.